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general description the max15014Cmax15017 combine a step-down dc-dc converter and a 50ma, low-quiescent-current low-dropout (ldo) regulator. the ldo regulator is ideal for powering always-on circuitry. the dc-dc converter input voltage range is 4.5v to 40v for the max15015/max15016, and 7.5v to 40v for the max15014/max15017. the dc-dc converter output is adjustable from 1.26v to 32v and can deliver up to 1a of load current. these devices utilize a feed-forward voltage-mode-control scheme for good noise immunity in the high-voltage switching environment and offer external compensation allowing for maximum flexibility with a wide selection of inductor values and capacitor types. the switching frequency is internally fixed at 135khz and 500khz, depending on the version chosen. moreover, the switch - ing frequency can be synchronized to an external clock signal through the sync input. light-load efficiency is improved by automatically switching to a pulse-skip mode. the soft-start time is adjustable with an external capacitor. the dc-dc converter can be disabled inde - pendent of the ldo, thus reducing the quiescent current to 47a (typ). the ldo linear regulators operate from 5v to 40v and deliver a guaranteed 50ma load current. the devices feature a preset output voltage of 5v (max1501_a) or 3.3v (max1501_b). alternatively, the output voltage can be adjusted from 1.5v to 11v by using an external resistive divider. the ldo section also features a reset output with adjustable timeout period. protection features include cycle-by-cycle current limit, hiccup-mode output short-circuit protection, and thermal shutdown. all devices are available in a space-saving, high-power (2.86w), 36-pin tqfn package and are rated for operation over the -40c to +125c automotive tem - perature range. applications mobile radios navigation systems features combined dc-dc converters and low-quiescent- current ldo regulators 1a dc-dc converters operate from 4.5v to 40v (max15015/max15016) or 7.5v to 40v (max15014/max15017) switching frequency of 135khz (max15014/max15016) or 500khz (max15015/max15017) 50ma ldo regulator operates from 5v to 40v independent of the dc-dc converter 47a quiescent current with dc-dc converter off and ldo on 6a system shutdown current frequency synchronization input shutdown/enable inputs adjustable soft-start time active-low open-drain reset output with programmable timeout delay thermal shutdown and output short-circuit protection space-saving (6mm x 6mm) thermally enhanced 36-pin tqfn package 19-0734; rev 1; 11/14 + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. part temp range pin-package max15014a atx+ -40c to +125c 36 tqfn-ep* max15014batx+ -40c to +125c 36 tqfn-ep* max15015a atx+ -40c to +125c 36 tqfn-ep* max15015batx+ -40c to +125c 36 tqfn-ep* max15016 aatx+ -40c to +125c 36 tqfn-ep* max15016batx+ -40c to +125c 36 tqfn-ep* max15017 aatx+ -40c to +125c 36 tqfn-ep* max15017batx+ -40c to +125c 36 tqfn-ep* max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators ordering information evaluation kit available downloaded from: http:///
in_sw, in_ldo, drain, en_sys, en_sw to sgnd ............................................................ -0.3v to +45v in_ldo to in_sw ................................................ -0.3v to +0.3v lx to sgnd ......................................... -0.3v to (v in_sw + 0.3v) lx to pgnd ........................................ .-0.3v to (v in_sw + 0.3v) bst to sgnd ....................................... -0.3v to (v in_sw + 12v) bst to lx .............................................................. -0.3v to +12v pgnd to sgnd .................................................... -0.3v to +0.3v reg, dvreg, sync, reset , ct to sgnd ....... -0.3v to +12v fb, comp_sw, ss to sgnd ................ -0.3v to (v reg + 0.3v) set_ldo, ldo_out to sgnd ............................ -0.3v to +12v c+ to pgnd (max15015/max15016 only) ............ (v dvreg - 0.3v) to 12v c- to pgnd (max15015/max15016 only) ........ -0.3v to (v dvreg + 0.3v) ldo_out output current ................................ internally limited switch dc current (drain and lx pins combined)t j = +125c ......................................................................... 1.9a t j = +150c ....................................................................... 1.25a reset sink current ............................................................ 5ma continuous power dissipation (t a = +70c) 36-pin tqfn (derate 26.3mw/c above +70c) single-layer board .................................................... 2105mw 36-pin tqfn (derate 35.7mw/c above +70c) multilayer board ......................................................... 2857mw operating temperature range ......................... -40c to +125c maximum junction temperature ..................................... +150c storage temperature range ............................ -60c to +150c lead temperature (soldering, 10s) ................................. +300c (v in_sw = v in_ldo = v drain = 14v, v en_sys = v en_sw = 2.4v, v reg = v dvreg , v sync = v set_ldo = v sgnd = v pgnd = 0v, c reg = 1f, c in_sw = 0.1f, c in_ldo = 0.1f, c ldo_out = 10f, c drain = 0.22f, t a = t j = -40c to +125c, unless otherwise noted. typical values are at t a = +25c.) (note 1) parameter symbol conditions min typ max units system supply current (not switching) i sys no load v fb = 1.3v, max15014/max15017 0.7 1.8 ma v fb = 1.3v, max15015/max15016 0.85 1.8 switching system supply current i sw no load v fb = 0v, max15014/ max15017 5.6 ma v fb = 0v, max15015/ max15016 8.6 ldo quiescent current i ldo v en_sys = 14v, v en_sw = 0v i ldo_out = 100a 47 63 a i ldo_out = 50ma 130 200 system shutdown current i shdn v en_sys = 0v, v en_sw = 0v 6 10 a system enable voltage v en_sysh en_sys = high, system on 2.4 v v en_sysl en_sys = low, system off 0.8 system enable hysteresis 220 mv system enable input current i en_sys v en_sys = 2.4v 0.5 2 a v en_sys = 14v 0.6 2 buck converter input voltage range v in_sw max15014/max15017 7.5 40.0 v max15015/max15016 4.5 40.0 max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators www.maximintegrated.com maxim integrated 2 absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics downloaded from: http:///
(v in_sw = v in_ldo = v drain = 14v, v en_sys = v en_sw = 2.4v, v reg = v dvreg , v sync = v set_ldo = v sgnd = v pgnd = 0v, c reg = 1f, c in_sw = 0.1f, c in_ldo = 0.1f, c ldo_out = 10f, c drain = 0.22f, t a = t j = -40c to +125c, unless otherwise noted. typical values are at t a = +25c.) (note 1) parameter symbol conditions min typ max units undervoltage lockout threshold uvlo th v in_sw and in_ldo rising, max15014/ max15017 6.7 7.0 7.4 v v in_sw and in_ldo rising, max15015/ max15016 3.90 4.08 4.25 undervoltage lockout hysteresis uvlo hyst max15014/max15017 0.54 v max15015/max15016 0.3 output voltage range v out minimum output 1.26 v maximum output 32 output current i out 1 a en_sw input voltage threshold v en_swh en_sw = high, switching power supply is on 2.4 v v en_swl en_sw = low, switching power supply is off 0.8 en_sw hysteresis 220 mv switching enable input current i en_sw v en_sw = 2.4v 0.5 2 a v en_sw = 14v 0.6 2 internal voltage regulator output voltage v reg max15014/max15017, v in_sw = 9v to 40v 7.6 8.4 v max15015/max15016, v in_sw = 5.5v to 40v 4.75 5.25 line regulation v in_sw = 9.0v to 40v, max15014/max15017 1 mv/v v in_sw = 5.5v to 40v, max15015/max15016 1 load regulation i reg = 0 to 20ma 0.25 v dropout voltage v in_sw = 7.5v (max15014/max15017), v in_sw = 4.5v (max15015/max15016), i reg = 20ma 0.5 v oscillator frequency range f clk v sync = 0v, max15014/max15016 122 136 150 khz v sync = 0v, max15015/max15017 425 500 575 maximum duty cycle d max v sync = 0v, v in_sw = 7.5v, max15014 (135khz) 90 98 % v sync = 0v, v in_sw = 4.5v, max15016 (135khz) 90 98 v sync = 0v, v in_sw = 4.5v, max15015 (500khz) 90 96 v sync = 0v, v in_sw = 7.5v, max15017 (500khz) 90 98 minimum lx low time v sync = 0v 94 ns sync high-level voltage 2.2 v sync low-level voltage 0.8 max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators www.maximintegrated.com maxim integrated 3 electrical characteristics (continued) downloaded from: http:///
(v in_sw = v in_ldo = v drain = 14v, v en_sys = v en_sw = 2.4v, v reg = v dvreg , v sync = v set_ldo = v sgnd = v pgnd = 0v, c reg = 1f, c in_sw = 0.1f, c in_ldo = 0.1f, c ldo_out = 10f, c drain = 0.22f, t a = t j = -40c to +125c, unless otherwise noted. typical values are at t a = +25c.) (note 1) parameter symbol conditions min typ max units sync frequency range f sync max15014/max15016 100 200 khz max15015/max15017 400 600 ramp level shift (valley) 0.3 v error amplifer soft-start reference voltage v ss 1.210 1.235 1.260 v soft-start current i ss v ss = 0v 7 12 17 a fb regulation voltage v fb 1.210 1.235 1.260 v fb input range v fb 0 1.5 v fb input current i fb v fb = 1.244v -250 +250 na comp voltage range i comp = -500a to +500a 0.25 4.5 v open-loop gain 80 db unity-gain bandwidth 1.8 mhz pwm modulator gain f sync = 500khz, max15015/max15017 10 v/v f sync = 135khz, max15014/max15016 10 current-limit comparator pulse skip threshold ipfm 100 200 300 ma cycle-by-cycle current limit i ilim 1.3 2 2.6 a number of consecutive ilim events to hiccup 7 hiccup timeout 512 clock periods power switch switch on-resistance v bst - v lx = 6v 0.15 0.4 0.80 ? switch gate charge v bst - v lx = 6v 4 nc switch leakage current v in_sw = v in_ldo = v lx = v drain = 40v, v fb = 0v 10 a bst quiescent current v bst = 40v, v drain = 40v, v fb = 0v, dvreg = 5v 400 600 a bst leakage current v bst = v drain = v lx = v in_sw = v in_ ldo = 40v, en_sw = 0v 1 a charge pump (max15015/max15016) c- output voltage low sinking 10ma 0.1 v c- output voltage high relative to dvreg, sourcing 10ma 0.1 v dvreg to c+ on-resistance sourcing 10ma 10 ? lx to pgnd on-resistance sinking 10ma 12 ? ldo input voltage range v in_ldo 5 40 v undervoltage lockout threshold uvlo_ldo th v in_ldo rising 3.90 4.1 4.25 v max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators www.maximintegrated.com maxim integrated 4 electrical characteristics (continued) downloaded from: http:///
(v in_sw = v in_ldo = v drain = 14v, v en_sys = v en_sw = 2.4v, v reg = v dvreg , v sync = v set_ldo = v sgnd = v pgnd = 0v, c reg = 1f, c in_sw = 0.1f, c in_ldo = 0.1f, c ldo_out = 10f, c drain = 0.22f, t a = t j = -40c to +125c, unless otherwise noted. typical values are at t a = +25c.) (note 1) parameter symbol conditions min typ max units undervoltage lockout hysteresis uvlo_ ldo hyst 0.3 v output current i out v in = 6v (note 2) 65 200 ma output voltage v ldo_out set_ldo = sgnd, max1501_a i ldo_out = 100a 4.90 5 5.06 v i ldo_out = 1ma 4.90 5 5.06 6v v in_ldo 40v, i ldo_out = 1ma 4.85 5 5.15 1ma i out 50ma, v in_ldo = 14v 4.85 5 5.15 set_ldo = sgnd, max1501_b i ldo_out = 100a 3.22 3.3 3.35 i ldo_out = 1ma 3.22 3.3 3.35 6v v in_ldo 40v, i ldo_out = 1ma 3.2 3.3 3.4 1ma i ldo_out 50ma, v in_ldo = 14v 3.2 3.3 3.4 adjustable output voltage range v adj v set_ldo > 0.25v 1.5 11.0 v dropout voltage v do v in_ldo = 5v, max1501_a i out = 10ma 0.6 v i out = 50ma 0.82 v in_ldo = 4.0v, max1501_b i out = 10ma 0.1 i out = 50ma 0.4 startup response time from en_sys high to ldo_out rise, r l = 500?, set_ldo = sgnd 400 s set_ldo reference voltage v set_ldo 1.220 1.241 1.265 v minimum set_ldo threshold (note 3) 185 mv set_ldo input leakage current i set_ldo v set_ldo = 11v 0.5 100 na power-supply rejection ratio psrr i out = 10ma, f = 100hz, 500mv p-p , v ldo_ out = 5v 78 db i out = 10ma, f = 1mhz, 500mv p-p , v ldo_ out = 5v 24 short-circuit current i sc 125 185 300 ma max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators www.maximintegrated.com maxim integrated 5 electrical characteristics (continued) downloaded from: http:///
(v in_sw = v in_ldo = v drain = 14v, v en_sys = v en_sw = 2.4v, v reg = v dvreg , v sync = v set_ldo = v sgnd = v pgnd = 0v, c reg = 1f, c in_sw = 0.1f, c in_ldo = 0.1f, c ldo_out = 10f, c drain = 0.22f, t a = t j = -40c to +125c, unless otherwise noted. typical values are at t a = +25c.) (note 1) note 1: limits at -40c are guaranteed by design and not production tested. note 2: maximum output current is limited by package power dissipation. note 3: this is the minimum voltage needed at set_ldo for the system to recognize that the user wants an adjustable ldo_out. parameter symbol conditions min typ max units reset output reset threshold v reset reset goes high after rising v ldo_out crosses this threshold 90 92.5 95 %v out reset output low voltage v rl (v ldo_out C v reset ) / i reset = 4k? 0.4 v reset output high leakage current i rh v reset = 3.3v (for max15_ _ _b), v reset = 5v (for max15_ _ _a) 1 a reset output minimum timeout period when ldo_out reaches reset threshold, ct = unconnected 50 s enable to reset minimum timeout period when en_sys goes high, c ldo_out = 10f, i ldo_out = 50ma, v ldo_out = 3.3v, ct = unconnected 650 s delay comparator threshold (rising) v ct-th 1.220 1.241 1.265 v delay comparator threshold hysteresis v ctth-hyst 100 mv ct charge current i ct-chq v ct = 0v 1.5 2 3 a ct discharge current i ct-dis 18 ma thermal shutdown thermal shutdown temperature temperature rising +160 c thermal shutdown hysteresis 20 c max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators www.maximintegrated.com maxim integrated 6 electrical characteristics (continued) downloaded from: http:///
(v in_sw = v in_ldo = v drain =14v, v en_sys = v en_sw = 2.4v, v reg = v dvreg , v sync = v set_ldo = v sgnd = v pgnd = 0v, c reg = 1f, c in_sw = 0.1f, c in_ldo = 0.1f, c ldo_out = 10 f, c drain = 0.22f, see figures 6 and 7, t a = +25c, unless otherwise noted.) switching frequency vs. temperature temperature (c) switching frequency (khz) max15014 toc02 -60 -40 -20 0 20 40 60 80 100 120 140 160 130 131 132 133 134 135 136 137 138 139 140 max15016a switching frequency vs. temperature temperature (c) switching frequency (khz) max15014 toc03 -60 -40 -20 0 20 40 60 80 100 120 140 160 450 460 470 480 490 500 510 520 530 max15015a maximum duty cycle vs. input voltage (max15016a) input voltage (v) maximum duty cycle (%) max15014 toc04 0 5 10 15 20 25 30 35 40 90 91 92 93 94 95 96 97 98 99 100 80 8482 8886 9290 94 9896 100 0 10 15 5 20 25 30 35 40 maximum duty cycle vs. input voltage (max15015a) max15014 toc05 input voltage (v) maximum duty cycle (%) error amplifier open-loop gain and phase vs. frequency frequency (hz) gain (db) max15014 toc06 60 100 140 180 220 260 300 340 -10 0 10 20 30 40 50 60 70 80 90 100 110 0.1 1 10 100 1k 10k 100k 1m 10m gain phase output current limit vs. input voltage input voltage (v) output current limit (a) max15014 toc07 0 10 20 30 40 50 0 0.5 1.0 1.5 2.0 2.5 t a = 0c t a = +25c t a = +85c t a = +135c system shutdown current vs. temperature temperature (c) system shutdown current (a) max15014 toc01 -50 0 50 100 150 0 1 2 3 4 5 6 7 8 9 10 max15016 2ms/div turn-on/-off waveform en_sw2v/div 0v0v v out 2v/div max15014 toc08 i load = 1a 2ms/div turn-on/-off waveform en_sw2v/div v out 2v/div max15014 toc09 i load = 100ma 0v0v max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators maxim integrated 7 www.maximintegrated.com typical operating characteristics downloaded from: http:///
(v in_sw = v in_ldo = v drain =14v, v en_sys = v en_sw = 2.4v, v reg = v dvreg , v sync = v set_ldo = v sgnd = v pgnd = 0v, c reg = 1f, c in_sw = 0.1f, c in_ldo = 0.1f, c ldo_out = 10 f, c drain = 0.22f, see figures 6 and 7, t a = +25c, unless otherwise noted.) 10ms/div turn-on/-off waveform increasing v in v in 5v/div v out 2v/div max15014 toc11 i load = 100ma 0v0v output voltage vs. temperature temperature (c) output voltage (v) max15014 toc12 -40 -15 10 35 60 85 110 135 3.20 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 3.40 i load = 1a i load = 0a efficiency vs. load current load current (ma) efficiency (%) max15014 toc13 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 v out = 3.3v v in = 4.5v v in = 7.5v v in = 12v v in = 24v v in = 40v max15016ai ldo_out = 0a 0 3020 10 40 50 60 70 80 90 100 1 10 100 1000 efficiency vs. load current (max15015a) max15014 toc14 load current (ma) efficiency (%) v out = 3.3v v in = 7.5v v in = 4.5v v in = 12v v in = 24v v in = 40v efficiency vs. load current (max15014) load current (ma) efficiency (%) max15014 toc15 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 v out = 5v v in = 24v v in = 40v v in = 12v v in = 7.5v efficiency vs. load current (max15017a) load current (ma) efficiency (%) max15014 toc16 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 v out = 5v v in = 24v v in = 40v v in = 12v v in = 7.5v 10ms/div turn-on/-off waveform increasing v in v in 5v/div v out 2v/div max15014 toc10 i load = 1a 0v0v 200s/div load-transient response v out ac-coupled100mv/div i load 500ma/div max15014 toc17 v in = 12v, i out = 0.25a to 1a max15015a 0 200s/div load-transient response v out ac-coupled100mv/div i load 500ma/div 0 max15014 toc18 v in = 4.5v, i out = 0.25a to 1a max15015a max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators maxim integrated 8 www.maximintegrated.com typical operating characteristics (continued) downloaded from: http:///
(v in_sw = v in_ldo = v drain =14v, v en_sys = v en_sw = 2.4v, v reg = v dvreg , v sync = v set_ldo = v sgnd = v pgnd = 0v, c reg = 1f, c in_sw = 0.1f, c in_ldo = 0.1f, c ldo_out = 10 f, c drain = 0.22f, see figures 6 and 7, t a = +25c, unless otherwise noted.) 2s/div lx voltage and inductor current v lx 5v/div inductor current500ma/div max15014 toc21 i load = 1a 0v 0 100 50 200150 350300 250 400 300 500 400 600 700 800 900 1000 minimum lx pulse width vs. load current max15014 toc22 load current (ma) lx pulse width (ns) v out = 3.3v ldo quiescent current vs. temperature temperature (c) ldo quiescent current (a) max15014 toc23 -50 -25 0 25 50 75 100 125 0 10 20 30 40 50 60 70 no load i load = 100a max15015b 2s/div lx voltage and inductor current v lx 5v/div 0v0v inductor current200ma/div max15014 toc19 i load = 40ma max150_ _ 2s/div lx voltage and inductor current v lx 5v/div 0v inductor current100ma/div max15014 toc20 i load = 160ma output voltage vs. temperature temperature (c) ldo output voltage (v) max15014 toc24 -40 -15 10 35 60 85 110 135 4.85 4.90 4.95 5.00 5.05 5.10 i load = 50ma i load = 1ma i load = 10ma max15015a output voltage vs. temperature temperature (c) ldo output voltage (v) max15014 toc25 -40 -15 10 35 60 85 110 135 3.23 3.24 3.25 3.26 3.27 3.28 3.29 3.30 3.31 i load = 50ma i load = 10ma i load = 1ma max15015b max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators maxim integrated 9 www.maximintegrated.com typical operating characteristics (continued) downloaded from: http:///
(v in_sw = v in_ldo = v drain =14v, v en_sys = v en_sw = 2.4v, v reg = v dvreg , v sync = v set_ldo = v sgnd = v pgnd = 0v, c reg = 1f, c in_sw = 0.1f, c in_ldo = 0.1f, c ldo_out = 10 f, c drain = 0.22f, see figures 6 and 7, t a = +25c, unless otherwise noted.) power-supply rejection ratio frequency (hz) psrr (db) max15014 toc27 -80 -70 -60 -50 -40 -30 -20 -10 0 10 0.1k 1k 10k 100k 1m 10m i ldo_out = 1ma i ldo_out = 10ma i ldo_out = 50ma 2ms/div turn-on/-off waveform toggling en_sys en_sys2v/div v out 2v/div max15014 toc28 i load = 50ma 0v0v 10ms/div turn-on/-off waveform toggling en_sys en_sys2v/div v out 2v/div max15014 toc29 r load = 1k ? 0v0v 10ms/div turn-on/-off waveform toggling en_sys en_sys2v/div v ldo_out 1v/div max15014 toc30 max15015br load = 66 ? 0v 0v 10ms/div turn-on/-off waveform toggling en_sys en_sys2v/div v ldo_out 1v/div max15014 toc31 0v 0v max15015br load = 660 ? 10ms/div turn-on/-off waveform increasing v in v in 5v/div v ldo_out 2v/div max15014 toc32 i load = 50ma 0v 0v dropout voltage vs. load current load current (ma) dropout voltage (mv) max15014 toc26 0 10 20 30 40 50 0 100 200 300 400 500 600 700 800 900 t a = -40c t a = +25c t a = +85c t a = +135c v in = 5v, i load = 0 to 50ma max15015a max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators maxim integrated 10 www.maximintegrated.com typical operating characteristics (continued) downloaded from: http:///
(v in_sw = v in_ldo = v drain =14v, v en_sys = v en_sw = 2.4v, v reg = v dvreg , v sync = v set_ldo = v sgnd = v pgnd = 0v, c reg = 1f, c in_sw = 0.1f, c in_ldo = 0.1f, c ldo_out = 10 f, c drain = 0.22f, see figures 6 and 7, t a = +25c, unless otherwise noted.) 10ms/div turn-on/-off waveform increasing v in v in 5v/div v ldo_out 1v/div max15014 toc35 0v 0v max15015br load = 660 ? 100s/div load-transient response v ldo_out ac-coupled100mv/div i load 20ma/div max15014 toc36 0 1ms/div input-voltage step response v in 20v/div v ldo_out ac-coupled100mv/div max15014 toc37 0v max15015bi load = 1ma 400ns/div residual switching noise on the ldo output v ldo_out 10mv/div max15014 toc38 dc-dc load = 1a 10ms/div ldo turn-on/-off waveform with increasing v in v in 2v/div v ldo_out 2v/div max15014 toc33 i load = 5ma 0v0v 10ms/div turn-on/-off waveform increasing v in v in 5v/div v ldo_out 1v/div max15014 toc34 0v 0v max15015br load = 66 ? max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators maxim integrated 11 www.maximintegrated.com typical operating characteristics (continued) downloaded from: http:///
pin name function max15014/ max15017 max15015/ max15016 1C3, 9, 12, 14, 16, 19, 24, 26, 27, 30, 35 1C3, 9, 12, 14, 16, 19, 24, 26, 27, 30, 35 n.c. no connection. not internally connected. leave unconnected or connect to sgnd. 23, 28 i.c. internally connected. leave unconnected. 4 4 reset active-low reset output. when the rising v ldo_out voltage crosses the reset threshold, reset goes high after an adjustable delay. pull up reset to ldo_out with at least 4k?. reset is an active-low open-drain output. 5 5 sgnd signal ground connection. connect sgnd and pgnd together at one point near the input bypass capacitor negative terminal. 6 6 ct reset timeout delay capacitor connection. ct is pulled low during reset. when out of reset, ct is pulled up to an internal 3.6v rail with a 2a current source. when the rising ct voltage reaches the trip threshold (typically 1.24v), reset is deasserted. when en_sys is low or in thermal shutdown, ct is low. 7 7 en_sw switching regulator enable input (active high). if en_sw is high and en_sys is high, the switching power supply is enabled. en_sw is internally pulled down to sgnd through a 0.5a current sink. 8 8 en_sys active-high system enable input. connect en_sys high to turn on the system. the ldo is active if en_sys is high; once en_sys is high, the switching regulator can be turned on if en_sw is high. en_sys is internally pulled down to sgnd through a 0.5a current sink. 10 10 set_ldo ldo feedback input/output voltage setting. connect set_ldo to sgnd to select the preset output voltage (5v or 3.3v). connect set_ldo to an external resistor- divider network for adjustable output operation. 11 11 ldo_ out linear regulator output. bypass with at least 10f low-esr capacitor from ldo_ out to sgnd. in the 5v ldo versions (a), the ldo operates in dropout below 6v down to the uvlo trip point. 13 13 in_ldo ldo input voltage. the input voltage range for the ldo extends from 5v to 40v. bypass with a 0.1f ceramic capacitor to sgnd. 15 15 bst high-side gate driver supply. connect bst to the cathode of the bootstrap diode and to the positive terminal of the bootstrap capacitor. 17, 18 17, 18 lx source connection of internal high-side switch. connect both lx pins to the inductor and the cathode of the freewheeling diode. 20, 21 20, 21 drain drain connection of the internal high-side switch. connect both drain inputs together. 22 22 pgnd power ground connection. connect the input bypass capacitor negative terminal, the anode of the freewheeling diode, and the output ilter capacitor negative terminal to pgnd. connect pgnd to sgnd together at a single point near the input bypass capacitor negative terminal. max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators www.maximintegrated.com maxim integrated 12 pin description downloaded from: http:///
pin name function max15014/ max15017 max15015/ max15016 23 c- charge-pump flying capacitor negative connection (max15015/max15016 only) 25 25 dvreg gate drive supply for the high-side mosfet driver. connect to reg and to the anode of the bootstrap diode for max15014/max15017. connect to reg for max15015/max15016. 28 c+ charge-pump flying capacitor positive connection (max15015/max15016 only). connect to the positive terminal of the external pump capacitor and to the anode of the bootstrap diode. 29 29 sync oscillator synchronization input. sync can be driven by an external clock to synchronize the switching frequency. connect sync to sgnd when not used. 31 31 comp error ampliier output. connect comp to the compensation feedback network. 32 32 fb feedback regulation point. connect to the center tap of a resistive divider from converter output to sgnd to set the output voltage. the fb voltage regulates to the voltage present at ss (1.235v). 33 33 ss soft-start and reference output. connect a capacitor from ss to sgnd to set the soft-start time. see the applications information section to calculate the value of the c ss capacitor. 34 34 reg internal regulator output. 5v output for the max15015/max15016 and 8v output for the max15014/max15017. bypass to sgnd with at least a 1f ceramic capacitor. 36 36 in_sw supply input connection. connect to in_ldo and an external voltage source from 4.5v to 40v. en_sw and en_sys must be high and in_sw must be above its uvlo threshold for operation of the switching regulator. ep exposed pad. the exposed pad must be electrically connected to sgnd. for an effective heatsinking, solder the exposed pad to a large copper plane. max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators www.maximintegrated.com maxim integrated 13 pin description (continued) downloaded from: http:///
detailed description the max15014Cmax15017 combine a voltage-mode buck converter with an internal 0.5 power-mosfet switch and a low-quiescent-current ldo regulator. the buck converter of the max15015/max15016 has a wide input voltage range of 4.5v to 40v. the max15014/ max15017s input voltage range is 7.5v to 40v. fixed switching frequencies of 135khz and 500khz are avail - able. the internal low r ds_on switch allows for up to 1a of output current, and the output voltage can be adjusted from 1.26v to 32v. external compensation and volt - age feed-forward simplify loop-compensation design and allow for a wide variety of l and c filter components. all devices offer an automatic switchover to pulse-skipping (pfm) mode, providing low-quiescent current and high efficiency at light loads. under no load, pfm mode opera - tion reduces the current consumption to 5.6ma for the max15014/max15017 and 8.6ma for the max15015/ max15016. in shutdown (dc-dc and ldo regulator off), the supply current falls to 6a. additional features include a programmable soft-start, cycle-by-cycle current limit, hiccup-mode output short-circuit protection, and thermal shutdown. the ldo linear regulator operates from 5v to 40v and delivers a guaranteed 50ma load current. the devices feature a preset output voltage of 5.0v (max1501_a) or 3.3v (max1501_b). alternatively, the output voltage can be adjusted from 1.5v to 11v using an external resistive divider. the ldo section also features a reset output with adjustable timeout period.enable inputs and uvlo the max15014Cmax15017 feature two logic inputs, en_sw (active-high) and en_sys (active-high) that can be used to enable the switching power supply and the ldo_out outputs. when v en_sw is higher than the threshold and en_sys is high, the switching power supply is enabled. when en_sys is high, the ldo is figure 1. max15015/max15016 simplified block diagram max15015max15016 pass element delay comparator v ref ref_ilim v ref tsd v ref i ss prereg shdn level shift reg_ldo high-side current sense dvreg logic overload management thermal shdn mux v int ramp in s/w + - + - + - ref_pfm clk overl + - ldo_outset_lod ct drain bst lx reset 185mv pgnd v int pclk v ref v intok v reg_en uvlo_ldo uvlo_sw enable ldo 0.925 x v ref vreg_ ok pfm en pfm vreg_ok v int v int v int vint - + v int in_ldo v int - + uvlo_ldo tsd shdn uvlo_sw tsd shdn v ref 2a out_ldo - + en_sys in_sw in_ldo pclk sclk dvreg ssa + - e/a + - - + + 0.3v clk - cpwm en osc v refok 4.1v v intok v refok 7.0v or 4.1v v intok ref v int v refok dvreg c+ c- reg en_sw ss fb comp sync sgnd max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators www.maximintegrated.com maxim integrated 14 downloaded from: http:///
active. when en_sys is low, the entire chip is off (see table 1). the max15014Cmax15017 provide undervoltage lockout (uvlo). the uvlo monitors the input voltage (v in_ldo ) and is fixed at 4.1v (max15015/max15016) or 7v (max15014/max15017). internal linear regulator (reg) reg is the output terminal of a 5v (max15015/ max15016), or 8v (max15014/max15017) ldo that is powered from in_sw and provides power to the ic. connect reg externally to dvreg to provide power for the high-side mosfet gate driver. bypass reg to sgnd with a ceramic capacitor (c reg ) of at least 1f. place the figure 2. max15014/max15017 simplified block diagram table 1. enable inputs configuration en_sys en_sw ldo regulator dc-dc switching converter low low off off low high off off high low on off high high on on max15014max15017 pass element delay comparator v ref ref_ilim v ref tsd v ref i ss prereg shdn reg_ldo high-side current sense dvreg logic overload management thermal shdn mux v int ramp in s/w + - + - + - ref_pfm clk overl + - ldo_outset_lod ct drain bst lx reset 185mv pgnd v int v ref v intok v reg_en uvlo_ldo uvlo_sw enable ldo 0.925 x v ref vreg_ ok pfm en pfm vreg_ok v int v int v int vint - + v int in_ldo v int - + uvlo_ldo tsd shdn uvlo_sw tsd shdn v ref 2a out_ldo - + en_sys in_sw in_ldo pclk sclk ssa + - e/a + - - + + 0.3v clk - cpwm en osc v refok 4.1v v intok v refok 7.0v or 4.1v v intok ref v int v refok reg en_sw ss fb comp sync sgnd ilim max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators www.maximintegrated.com maxim integrated 15 downloaded from: http:///
capacitor physically close to the max15014Cmax15017 to provide good bypassing. during normal operation, reg is intended for powering up only the internal circuitry and should not be used to supply power to external loads. soft-start and reference (ss) ss is the 1.235v reference bypass connection for the max15014Cmax15017 and also controls the soft-start period. at startup, after input voltage is applied at in_sw, in_ldo and the uvlo thresholds are reached, the device enters soft-start. during soft-start, 14a is sourced into the capacitor (c ss ) connected from ss to sgnd causing the reference voltage to ramp up slowly. when v ss reaches 1.244v, the output becomes fully active. set the soft-start time (t ss ) using following equation: ss ss ss ss vc t i = where v ss = soft-start reference voltage = 1.235v (typ), i ss = soft-start current = 14 x 10 -6 a (typ), t ss is in seconds and c ss is in farads. internal charge pump (max15015/max15016) the max15015/max15016 feature an internal charge pump to enhance the turn-on of the internal mosfet, allowing for operation with input voltages down to 4.5v. connect a flying capacitor (c f ) between c+ and c-, a boost diode from c+ to bst, as well as a bootstrap capacitor (c bst ) between bst and lx to provide the gate-drive voltage for the high-side n-channel dmos switch. during the on-time, the flying capacitor is charged to v dvreg . during the off-time, the positive terminal of the flying capacitor (c+) is pumped to two times v dvreg , and charge is dumped onto c bst to provide twice the regulator voltage across the high-side dmos driver. use a ceramic capacitor of at least 0.1f for c bst and c f , located as close as possible to the device.gate-drive supply (dvreg) dvreg is the supply input for the internal high-side mosfet driver. the power for dvreg is derived from the output of the internal regulator (reg). connect dvreg to reg externally. to filter the switching noise, the use of an rc filter (1 and 0.47f) from reg to dvreg is recommended. in the max15015/max15016, the high-side drive supply is generated using the inter - nal charge pump along with the bootstrap diode and capacitor. in the max15014/max15017, the high-side mosfet driver supply is generated using only the boot - strap diode and capacitor. error ampliier the output of the internal error amplifier (comp) is avail - able for frequency compensation (see the compensation design section). the inverting input is fb, the noninvert - ing input ss, and the output comp. the error amplifier has an 80db open-loop gain and a 1.8mhz gbw product. see the typical operating characteristics for the gain and phase vs. frequency graph. oscillator/synchronization input (sync) with sync connected to sgnd, the max15014C max15017 use their internal oscillator and switch at a fixed frequency of 135khz and 500khz. the max15014/ max15016 are the 135khz options and max15015/ max15017 are the 500khz options. for external synchro - nization, drive sync with an external clock from 400khz to 600khz (max15015/max15017), or 100khz to 200khz (max15014/max15016). when driven with an external clock, the device synchronizes to the rising edge of sync. pwm comparator/voltage feed-forward an internal ramp generator clocked by the internal oscillator is compared against the output of the error amplifier to generate the pwm signal. the maximum amplitude of the ramp (v ramp ) automatically adjusts to compensate for input voltage and oscillator frequency changes. this causes the v in_sw /v ramp to be a con - stant 10v/v across the input voltage range of 4.5v to 40v (max15015/max15016), or 7.5v to 40v (max15014/ max15017), and the sync frequency range of 400khz to 600khz (max15015/max15017), or 100khz to 200khz (max15014/max15016). output short-circuit protection (hiccup mode) the max15014Cmax15017 protect against an output short circuit by utilizing hiccup-mode protection. in hiccup mode, a series of sequential cycle-by-cycle current-limit events cause the part to shut down and restart with a soft- start sequence. this allows the device to operate with a continuous output short circuit. during normal operation, the current is monitored at the drain of the internal power mosfet. when the current limit is exceeded, the internal power mosfet turns off until the next on-cycle and a counter increments. if the counter counts seven consecutive current-limit events, the device discharges the soft-start capacitor and shuts down for 512 clock periods before restarting with a soft-start sequence. each time the power mosfet turns on and the device does not exceed the current limit, the counter is reset. max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators www.maximintegrated.com maxim integrated 16 downloaded from: http:///
ldo regulator the ldo regulator operates over an input voltage from 5v to 40v, and can be enabled independently of the dc-dc converter section. its quiescent current is as low as 47a with a load current of 100a. all devices feature a preset output voltage of 5v (max1501_a) or 3.3v (max1501_b). alternatively, the output voltage can be adjusted using an external resistive-divider network connected between ldo_out, set_ldo, and sgnd. see figure 5. reset output the reset output is typically connected to the reset input of a microprocessor (p). a ps reset input starts or restarts the p in a known state. the max15014C max15017 supervisory circuits provide the reset logic to prevent code-execution errors during power-up, power- down, and brownout conditions. reset changes from high to low whenever the monitored voltage drops below the reset threshold voltage. once the monitored volt - age exceeds its respective reset threshold voltage(s), reset remains low for the reset timeout period, then goes high. the reset timeout period is adjustable with an external capacitor (c ct ) connected to ct. thermal-shutdown protection the max15014Cmax15017 feature thermal-shutdown protection that limits the total power dissipation in the device and protects it in the event of an extended thermal-fault condition. when the die temperature exceeds +160c, an internal thermal sensor shuts down the part, turning off the dc-dc converter and the ldo regulator, and allowing the ic to cool. after the die temperature falls by 20c, the part restarts with a soft-start sequence. applications information setting the output voltage connect a resistive divider (r3 and r4, see figures 6 and 7) from out to fb to sgnd to set the output voltage. choose r3 and r4 so that dc errors due to the fb input bias current do not affect the output-voltage setting precision. for the most common output-voltage settings (3.3v or 5v), r3 values in the 10k range are adequate. select r3 first and calculate r4 using the following equation: out fb r3 r4 v 1 v = ?? ? ?? ?? where v fb = 1.235v. inductor selectionthree key inductor parameters must be speci - fied for operation with the max15014Cmax15017: inductance value (l), peak inductor current (i peak ), and inductor saturation current (i sat ). the minimum required inductance is a function of operating frequency, input- to-output voltage differential, and the peak-to-peak inductor current (i p-p ). higher i p-p allows for a lower inductor value, while a lower i p-p requires a higher inductor value. a lower inductor value minimizes size and cost and improves large-signal and transient response, but reduces efficiency due to higher peak currents and higher peak-to-peak output-voltage ripple for the same output capacitor. on the other hand, higher inductance increases efficiency by reducing the i p-p . resistive losses due to extra wire turns can exceed the ben - efit gained from lower i p-p levels, especially when the inductance is increased without also allowing for larger inductor dimensions. a good compromise is to choose i p-p equal to 40% of the full load current. calculate the inductor using the following equation: out in out in sw p p v (v v ) l vf i ? ? = ? v in and v out are typical values so that efficiency is optimum for typical conditions. the switching frequency (f sw ) is internally fixed at 135khz (max15014/max15016) or 500khz (max15015/max15017) and can vary when synchronized to an external clock (see the oscillator/ synchronization input (sync) section). the i p-p , which reflects the peak-to-peak output ripple, is worst at the maxi - mum input voltage. see the output capacitor selection section to verify that the worst-case output ripple is accept - able. the inductor current (i sat ) is also important to avoid current runaway during continuous output short circuit. select an inductor with an i sat specification higher than the maximum peak current limit of 2.6a.input capacitor selection the discontinuous input current of the buck converter causes large input ripple currents and therefore the input capacitor must be carefully chosen to keep the input voltage ripple within design requirements. the input volt - age ripple is comprised of v q (caused by the capacitor discharge) and v esr (caused by the esr of the input capacitor). the total voltage ripple is the sum of v q and v esr . calculate the input capacitance and esr required for a specified ripple using the following equations: max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators www.maximintegrated.com maxim integrated 17 downloaded from: http:///
esr pp out_max out_max in q sw v esr i i 2 id c vf ? ? = ? + = ? where c in is the sum of c drain and additional decoupling capacitance at the buck converter input, in out out pp in sw out in (v v ) v i and vf l v d v ? ? ?= = i out_max is the maximum output current, d is the duty cycle, and f sw is the switching frequency. the max15014Cmax15017 include uvlo hysteresis and soft-start to avoid chattering during turn-on. however, use additional bulk capacitance if the input source impedance is high. use enough input capacitance at lower input voltages to avoid possible undershoot below the undervoltage-lockout threshold during transient loading. output capacitor selection the allowable output-voltage ripple and the maximum deviation of the output voltage during load steps deter - mine the output capacitance (c out ) and its equivalent series resistance (esr). the output ripple is mainly composed of vq (caused by the capacitor discharge) and v esr (caused by the voltage drop across the esr of the output capacitor). the equations for calculating the peak-to-peak output-voltage ripple are: pp q out sw esr p p i v 8c f v esr i ? ? ? ?= ? = ? normally, a good approximation of the output-voltage ripple is v ripple = v esr + v q . if using ceramic capacitors, assume the contribution to the output-voltage ripple from esr and the capacitor discharge to be equal to 20% and 80%, respectively. i p-p is the peak-to- peak inductor current (see the input capacitor selection section) and f sw is the converters switching frequency. the allowable deviation of the output voltage during fast- load transients also determines the output capacitance, its esr, and its equivalent series inductance (esl). the output capacitor supplies the load current during a load step until the controller responds with a greater duty cycle. the response time (t response ) depends on the closed-loop bandwidth of the converter (see the compensation design section). the resistive drop across the output capacitors esr, the drop across the capacitors esl (v esl ), and the capacitor discharge causes a voltage droop during the load step. use a combination of low-esr tantalum/aluminum electrolytic and ceramic capacitors for better transient load and voltage-ripple performance. non-leaded capacitors and capacitors in parallel help reduce the esl. keep the maximum output-voltage deviation below the tolerable limits of the electronics being powered. use the following equations to calculate the required esr, esl, and capacitance value during a load step: esr step step response out q esl step step response c v esr i it c v vt esl i 1 t 3 ? ? = = ? ? = ? where i step is the load step, t step is the rise time of the load step, t response is the response time of the controller, and f c is the closed-loop crossover frequency. compensation design the max15014Cmax15017 use a voltage-mode-control scheme that regulates the output voltage by comparing the error-amplifier output (comp) with an internal ramp to produce the required duty cycle. the output lowpass lc filter creates a double pole at the resonant frequency, which has a gain drop of -40db/decade. the error ampli - fier must compensate for this gain drop and phase shift to achieve a stable closed-loop system. the basic regulator loop consists of a power modulator, an output feedback-divider, and a voltage error amplifier. the power modulator has a dc gain set by v in /v ramp , with a double pole and a single zero set by the output inductance (l), the output capacitance (c out ), and its esr. the power modulator incorporates a voltage feed- forward feature, which automatically adjusts for variations in the input voltage, resulting in a dc gain of 10. max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators www.maximintegrated.com maxim integrated 18 downloaded from: http:///
the following equations define the power modulator: in mod_dc ramp lc out zesr out v g 10 v 1 f 2 lc 1 f 2 c esr = = = = the switching frequency is internally set at 500khz for max15015/max15017 and can vary from 400khz to 600khz when driven with an external sync signal. the switching frequency is internally set at 135khz for max15014/max15016 and can vary from 100khz to 200khz when driven with an external sync signal. the crossover frequency (f c ), which is the frequency when the closed-loop gain is equal to unity, should be set to around 1/10 of the switching frequency or below. the crossover frequency occurs above the lc double-pole frequency, and the error amplifier must provide a gain and phase bump to compensate for the rapid gain and phase loss from the lc double pole, which exhibits little damping. this is accomplished by utilizing a type 3 compensator that introduces two zeroes and three poles into the control loop. the error amplifier has a low-frequency pole (f p1 ) near the origin so that tight voltage regulation at dc can be achieved. the two zeroes are at: zi 1 f 2 r5 c7 = and z2 1 f 2 (r3 r6) c6 = + and the higher frequency poles are at: p2 1 f 2 r6 c6 = and p3 1 f c7 c8 2 r5 c7 c8 = + the compensation design primarily depends on the type of output capacitor. ceramic capacitors exhibit very low esr, and are well suited for high-switching-frequency applications, but are limited in capacitance value and tend to be more expensive. aluminum electrolytic capaci - tors have much larger esr but can reach much larger capacitance values. compensation when f c < f zesr this is usually the case when a ceramic capacitor is selected. in this case, f zesr occurs after f c . figure 3 shows the error amplifier feedback as well as its gain response. f z1 is set to 0.5 to 0.8 x f lc and f z2 is set to f lc to compensate for the gain and phase loss due to the double pole. to achieve a 0db crossover with -20db/decade slope, poles f p2 and f p3 are set above the crossover frequency (f c ). the values for r3 and r4 are already determined in the setting the output voltage section. the value of r3 is also used in the following calculations. since f z2 < f c < f p2 , then r3 >> r6, and r3 + r6 can be approximated as r3. now we can calculate c6 for zero f z2 : lc 1 c6 2 f r3 = figure 3. error amplifier compensation circuit (closed-loop and error-amplifier gain plot) for ceramic capacitors gain (db) v out ref r3 comp r6 r5 c6 r4 frequency closed-loopgain eagain f z1 f z2 f c f p2 f p3 c8 ea c7 max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators www.maximintegrated.com maxim integrated 19 downloaded from: http:///
f c occurs between f z2 and f p2 . in this region, the compensatorgain (g ea ) at f c is due primarily to c6 and r5. therefore, g ea (f c ) = 2 x f c x c6 x r5 and the modulator gain at f c is: mod_dc mod c 2 c out g g (f ) (2 f ) l c = since g ea (f c ) x g mod (f c ) = 1, r5 is calculated by: c out mod_dc f lc 2 r5 c6 g = the frequency of f z1 is set to 0.5 x f lc and now we can calculate c7 by: lc 1 c7 0.5 2 r5 f = f p2 is set at 1/2 the switching frequency (f sw ). r6 is then calculated by: sw 1 r6 2 c6 (0.5 f ) = note that if the crossover frequency has been chosen as 1/10 of the switching frequency, then f p2 = 5xf c . the purpose of f p3 is to further attenuate the residual switching ripple at the comp pin. if the esr zero (f zesr ) occurs in a region between f c and f sw /2, then f p3 can be used to cancel it. this way, the bode plot of the loop-gain plot does not flatten out soon after the 0db crossover, and maintains its -20db/decade slope up to 1/2 of the switching frequency. if the esr zero well exceeds f sw /2 (or even f sw ), f p3 should in any case be set high enough not to erode the phase margin at the crossover frequency. for example, it can be set between 5 x f c and 10 x f c . the value for c8 is calculated from: p3 c7 c8 ( 2 c7 r 5 f 1) = ? compensation when f c > f zesr for larger esr capacitors such as tantalum and aluminum electrolytic, f zesr can occur before f c . if f zesr < f c , then f c occurs between f p2 and f p3 . f z1 and f z2 remain the same as before; however, f p2 is now set equal to f zesr . the output capacitors esr zero frequency is higher than f lc but lower than the closed-loop crossover frequency. the equations that define the error amplifiers poles and zeros (f z1 , f z2 , f p2 , and f p3 ) are the same as before; however, f p2 is now lower than the closed-loop crossover frequency. figure 4 shows the error-amplifier feedback as well as its gain response for circuits that use higher-esr output capacitors (tantalum or aluminum electrolytic). again, starting from r3, calculate c6 for zero f z2 : lc 1 c6 2 f r3 = and then place f p2 to cancel the esr zero. r6 is calculated as: out c esr r6 c6 = if the value obtained here for r6 is not considerably smaller than r3, recalculate c6 using (r3 + r6) in place of r3. then use the new value of c6 to obtain a better approximation for r6. the process can be further iterated, and convergence is ensured as long as f lc < f zesr . figure 4. error amplifier compensation circuit (closed- loop and error-amplifier gain plot) for higher esr output capacitors gain (db) v out ref r3 comp r6 r5 c6 r4 frequency closed-loopgain eagain f z1 f z2 f c f p2 f p3 c8 ea c7 max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators www.maximintegrated.com maxim integrated 20 downloaded from: http:///
the error-amplifier gain between f p2 and f p3 is approxi - mately equal to r5/(r6 || r3). the esr zero frequency (f zesr ) might not be very much higher than the double-pole frequency f lc ; therefore, the value of r5 can be calculated as: 2 c 2 mod_dc lc f r3 r6 r5 r3 r6 gf = + c7 can still be calculated as: lc 1 c7 0.5 2 r5 f = f p3 is set at 5xf c . therefore, c8 is calculated as: p3 c7 c8 2 c7 r5 f 1 = ? setting the ldo linear regulator output voltage the max15014Cmax15017 ldo regulator features dual mode? operation: it can operate in either a preset volt - age mode or an adjustable mode. in preset-voltage mode, internal trimmed feedback resistors set the internal linear regulator to 3.3v or 5v (see the selector guide ). select preset-voltage mode by connecting set_ldo to ground. in adjustable mode, select an output voltage between 1.5v and 11v using two external resistors connected as a voltage-divider to set_ldo (see figure 5). set the output voltage using the following equation: out set_ldo r1 vv 1 r2 ?? = + ???? where v set_ldo = 1.241v and the recommended value for r2 is around 50k. setting the reset timeout delay the reset timeout period is adjustable to accommodate a variety of p applications. adjust the reset timeout period by connecting a capacitor (c ct ) between ct and sgnd. = - ct th ct rp - ct thq cv t i where v ct-th = delay-comparator threshold (rising) = 1.241v (typ), i ct-thq = ct charge current = 2 x 10 -6 a (typ), t rp is in seconds and c ct is in farads. connect ct to ldo_out to select the internally fixed timeout period. c ct must be a low-leakage-type capacitor. ceramic capacitors are recommended; do not use capacitors lower than 200pf to avoid the influence of parasitic capacitances. capacitor selection and regulator stability for stable operation over the full temperature range and with load currents up to 50ma, use a 10f (min) output capacitor (c ldo_out ) with a maximum esr of 0.4. to reduce noise and improve load-transient response, stability, and power-supply rejection, use larger output capacitor values. some ceramic dielectrics such as z5u and y5v exhibit very large capacitance and esr variation with temperature and are not recommended. with x7r or x5r dielectrics, 15f should be sufficient for operation over their rated temperature range. for higher esr tantalum capacitors (up to 1), use 22f or more to maintain stability. to improve power-supply rejection and transient response, use a minimum 0.1f capacitor between in_ldo and sgnd. power dissipation the max15014Cmax15017 are available in a thermally enhanced package and can dissipate up to 2.86w at t a = +70c. when the die temperature reaches +160c, the part shuts down and is allowed to cool. after the die cools by 20c, the device restarts with a soft-start. the power dissipated in the device is the sum of the power dissipated in the ldo, power dissipated from supply current (p q ), transition losses due to switching the internal power mosfet (p sw ), and the power dual mode is a trademark of maxim integrated products, inc. figure 5. setting the output voltage using a resistive divider max15014C max15017 ldo_out set_ldo r2 r1 sgnd in_ldo v in_ldo max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators www.maximintegrated.com maxim integrated 21 downloaded from: http:///
dissipated due to the rms current through the internal power mosfet (p mosfet ). the total power dissipated in the package must be limited such that the junction temperature does not exceed its absolute maximum rating of +150c at maximum ambient temperature. calculate the power lost in the max15014Cmax15017 using the following equations: the power loss through the switch: mosfet rms_mosfet on 22 rms_mosfet pk pk dc dc pp pk out pp dc out out in 2 p (i ) r d i i (i i ) i 3 i ii 2 i ii 2 v d v ? ? = ?? = ++ ?? ?? ? = + ? = ? = r on is the on-resistance of the internal power mosfet (see the electrical characteristics ). the power loss due to switching the internal mosfet: in out r f sw sw v i (t t ) f p 4 + = t r and t f are the rise and fall times of the internal power mosfet measured at lx. the power loss due to the switching supply current (i sw ): p q = v in_sw i sw the power loss due to the ldo regulator: p ldo = (v in_ldo ? v ldo_out ) i ldo_out the total power dissipated in the device will be: p total = p mosfet + p sw + p q + p ldo figure 6. max15015/max15016 typical application circuit (4.5v to 40v input operation) max15015max15016 sgnd sgnd set_ldo 0.47f c reg 1 ? pgnd pgnd r5 c7 dvreg r4 r3 c- c+ fb comp c in_sw c drain c in_ldo en_sys en_swreg sync ss c ss r6 c6 ct c f v in 5v to 40v reset ldo_out c ct d2 c bst 10k ? c ldo_out v out2 at 50ma lx bst c out v out1 at 1a l in_sw drain d1 in_ldo c8 v in 4.5v to 40v max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators www.maximintegrated.com maxim integrated 22 downloaded from: http:///
figure 7. max15014/max15017 typical application circuit (7.5v to 40v input-voltage operation) max15014max15017 sgnd sgnd set_ldo 0.47f c reg 1 pgnd pgnd r5 c7 dvreg r4 r3 fb comp c in_sw c drain c in_ldo en_sys en_swreg sync ss c ss r6 c6 ct v in 7.5v to 40v reset ldo_out c ct d2 c bst 10k ? c ldo_out v out2 at 50ma lx bst c out v out1 at 1a l in_sw drain d1 in_ldo c8 v in 7.5v to 40v max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators www.maximintegrated.com maxim integrated 23 downloaded from: http:///
part switching frequency (khz) dc-dc minimum input voltage (v) charge pump ldo output 5v 3.3v adjustable output max15014a 135 7.5 x x max15014b 135 7.5 x x max15015a 500 4.5 x x x max15015b 500 4.5 x x x max15016a 135 4.5 x x x max15016b 135 4.5 x x x max15017a 500 7.5 x x max15017b 500 7.5 x x package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 36 tqfn t3666+3 21-0141 90-0050 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 3635 34 33 32 31 30 29 28 2726 25 24 23 22 21 20 19 + tqfn max15014C max15017 top view set_ldo ldo_out n.c. in_ldo n.c. bst n.c. lx lx n.c. drain drain pgnd c- (i.c.) n.c. dvreg n.c. n.c. n.c. reg n.c. sync ss fb comp in_sw n.c.n.c. n.c. reset sgnd ct en_sw en_sys n.c. c+ (i.c.) *ep = exposed pad. ep* ( ) max15014/max15017 max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators www.maximintegrated.com maxim integrated 24 chip information process: bicmos/dmos pin conigurationselector guide downloaded from: http:///
revision number revision date description pages changed 0 1/07 initial release 1 11/14 no /v opns in ordering information ; deleted automotive reference in applications section; update packaging information 1, 25 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max15014Cmax15017 1a, 4.5v to 40v input buck converters with 50ma auxiliary ldo regulators ? 2014 maxim integrated products, inc. 25 revision history for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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